A practical approach for circuit routing on dynamic reconfigurable devices

Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial re configurability is a new challenging problem. A network-on-chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.

[1]  Jürgen Teich,et al.  A Dynamic NoC Approach for Communication in Reconfigurable Devices , 2004, FPL.

[2]  John Wawrzynek,et al.  Hardware-assisted fast routing , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[3]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[4]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[5]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[6]  Hartmut Schmeck,et al.  RMB-a reconfigurable multiple bus network , 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.

[7]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[8]  Jürgen Teich,et al.  Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices , 2004, FPL.

[9]  Adronis Niyonkuru,et al.  Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs , 2004, FPL.

[10]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.