Weighted logic locking: A new approach for IC piracy protection

Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance-HD-compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit's values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly “generic” and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).

[1]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[2]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.

[3]  Jeyavijayan Rajendran,et al.  Logic encryption: A fault analysis perspective , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[5]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[6]  Giorgio Di Natale,et al.  A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[7]  Igor L. Markov,et al.  Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Nur A. Touba,et al.  Improving logic obfuscation via logic cone analysis , 2015, 2015 16th Latin-American Test Symposium (LATS).

[9]  Ramesh Karri,et al.  On Improving the Security of Logic Locking , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Ozgur Sinanoglu,et al.  SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).