Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design

[1]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[2]  Tughrul Arslan,et al.  VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond , 2007, 2007 Asia and South Pacific Design Automation Conference.

[3]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[4]  G. David Forney,et al.  Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference , 1972, IEEE Trans. Inf. Theory.

[5]  R. Cumplido,et al.  A Runtime Reconfigurable Architecture for Viterbi Decoding , 2006, 2006 3rd International Conference on Electrical and Electronics Engineering.

[6]  Norbert Wehn,et al.  A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment , 2008, 2008 Design, Automation and Test in Europe.

[7]  An-Yeu Wu,et al.  Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Andrew J. Viterbi,et al.  An Intuitive Justification and a Simplified Implementation of the MAP Decoder for Convolutional Codes , 1998, IEEE J. Sel. Areas Commun..

[9]  Ran-Hong Yan,et al.  A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[10]  Roy Paily,et al.  Low power Viterbi Decoder by modified ACSU architecture and clock gating method , 2011, 2011 International Conference on Communications and Signal Processing.

[11]  Patrick Robertson,et al.  Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding , 1997, Eur. Trans. Telecommun..

[12]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[13]  An-Yeu Wu,et al.  VLSI design of dual-mode Viterbi/turbo decoder for 3GPP , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[14]  Joseph R. Cavallaro,et al.  Viturbo: a reconfigurable architecture for Viterbi and turbo decoding , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..