Symmetry Constraint for Analog Layout with CBL Representation

In the design of analog circuits, some pairs of devices are constrained to be placed symmetrically with respect to a common axis in order to cope with the device matching. In this paper, symmetry constraint is coped with CBL representation. In our algorithm, the incompleteness and redundancy of CBL can be corrected. And the experimental results show the effectiveness of our method

[1]  Florin Balasa,et al.  Efficient solution space exploration based on segment trees in analog placement with symmetry constraints , 2002, ICCAD 2002.

[2]  Florin Balasa.  Modeling non-slicing floorplans with binary trees , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  X. Hong,et al.  Constraints generation for analog circuits layout , 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

[4]  Florin Balasa,et al.  Symmetry within the sequence-pair representation in the context ofplacement for analog design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  Automation of IC layout with analog constraints , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Georges Gielen,et al.  A performance-driven placement tool for analog integrated circuits , 1995 .

[7]  Yici Cai,et al.  Corner block list representation and its application to floorplan optimization , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Yao-Wen Chang,et al.  Placement with symmetry constraints for analog layout design using TCG-S , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[9]  Rob A. Rutenbar,et al.  KOAN/ANAGRAM II: new tools for device-level analog placement and routing , 1991 .