An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs

Due to recent technology scaling trends and increased circuit complexity, process and runtime variabilities are becoming major threats for correct circuit operation. Among these, transient voltage fluctuations appear to be the most critical issue, accounting for the biggest component of timing margin, at increased cost. As various design and workload parameters have an impact on voltage fluctuations, they need to be fully understood in order to design efficient countermeasures and margining. Field-programmable gate arrays are predestined for this analysis by allowing more control over such experiments at lower cost than application-specific integrated circuits. Furthermore, they highly suffer from the same issues, which are typically only handled by excessive and overpessimistic timing margining built into the mapping tools. In this paper, we implemented and calibrated sensors in configurable logic appropriate to observe delay changes caused by transient voltage fluctuations. We place them at multiple locations on the chip to evaluate temporal and spatial changes in a timing margin due to different workload characteristics. Moreover, we analyze the spatial and the temporal interdependence of various workloads and investigate their combined effect on a voltage drop. This analysis provides useful insights to designers for application mapping and workload scheduling.

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