High-speed CMOS-to-ECL pad driver in 0.18 /spl mu/m CMOS

In this paper, we present a CMOS-to-ECL converter and pad driver, to provide true negative ECL outputs from a positive-supply CMOS ASIC. The circuit exploits negative feedback loops to precisely set the output voltages corresponding to 0 and 1 logic ECL levels, and a high speed current switch to allow a bit rate of hundreds of Mb/s. Simulations using 0.18 /spl mu/m CMOS technology show a bit-rate in excess of 1 Gb/s, with high tolerance to temperature, load resistance and capacitance values.

[1]  W. Rajan,et al.  A reliable 5V OTA in 3.3V CMOS technology , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[2]  Stanley E. Schuster,et al.  Fast CMOS ECL receivers with 100-mV worst-case sensitivity , 1988 .

[3]  Jan Sevenhans,et al.  ECL-CMOS and CMOS-ECL interface in 1.2- mu m CMOS for 150-MHz digital ECL data transmission systems , 1991 .

[4]  T. G. Noll,et al.  A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[5]  Bogdan M. Wilamowski,et al.  A low voltage to high voltage level shifter circuit for MEMS application , 2003, Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488).

[6]  Evert Seevinck,et al.  CMOS subnanosecond true-ECL output buffer , 1990 .

[7]  A. Boni.  1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-/spl mu/m CMOS , 2001 .

[8]  C.A.T. Salama,et al.  Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS , 1999, IEEE J. Solid State Circuits.

[9]  E. De Man,et al.  A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems , 1988 .