Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs
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[1] Reiner W. Hartenstein,et al. Coarse grain reconfigurable architecture (embedded tutorial) , 2001, ASP-DAC '01.
[2] Valeria Bertacco,et al. Human computing for EDA , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[3] C. Sunstein. Infotopia: How Many Minds Produce Knowledge , 2006 .
[4] John Wawrzynek,et al. Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[5] Carl Ebeling,et al. RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.
[6] Diederik Verkest,et al. Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor , 2008, 21st International Conference on VLSI Design (VLSID 2008).
[7] Vaishali Tehre,et al. Survey on Coarse Grained Reconfigurable Architectures , 2012 .
[8] André DeHon,et al. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[9] Yao-Wen Chang,et al. NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs , 2005, ISPD '05.
[10] John Langford,et al. Telling humans and computers apart automatically , 2004, CACM.
[11] Menno D. T. de Jong,et al. Does think aloud work?: how do we know? , 2006, CHI Extended Abstracts.
[12] Tracy Fullerton,et al. Game Design Workshop: A Playcentric Approach to Creating Innovative Games, Third Edition , 2014 .
[13] Jarrod A. Roy,et al. Unification of partitioning, placement and floorplanning , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[14] Colin Norman. 2011 International Science & Engineering Visualization Challenge. , 2012, Science.
[15] Wayne Luk,et al. Harnessing Human Computation Cycles for the FPGA Placement Problem , 2009, ERSA.
[16] Pietro Michelucci,et al. Handbook of Human Computation , 2013, Springer New York.
[17] Manuel Blum,et al. Improving accessibility of the web with a computer game , 2006, CHI.
[18] A. Sangiovanni-Vincentelli,et al. The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.
[19] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.
[20] Kiyoung Choi,et al. Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[21] Krunalkumar Patel,et al. On fast iterative mapping algorithms for stripe based coarse-grained reconfigurable architectures , 2015 .
[22] Laura A. Dabbish,et al. Designing games with a purpose , 2008, CACM.
[23] Carl Ebeling,et al. SPR: an architecture-adaptive CGRA mapping tool , 2009, FPGA '09.
[24] Kiyoung Choi. Coarse-Grained Reconfigurable Array: Architecture and Application Mapping , 2011, IPSJ Trans. Syst. LSI Des. Methodol..
[25] Laura A. Dabbish,et al. Labeling images with a computer game , 2004, AAAI Spring Symposium: Knowledge Collection from Volunteer Contributors.
[26] Kunle Olukotun,et al. REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .
[27] Jianwen Zhu,et al. Towards scalable placement for FPGAs , 2010, FPGA '10.
[28] Taraneh Taghavi,et al. Dragon2005: large-scale mixed-size placement tool , 2005, ISPD '05.
[29] João M. P. Cardoso,et al. A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[30] Valeria Bertacco. Humans for EDA and EDA for humans , 2012, DAC Design Automation Conference 2012.
[31] Muhammad Shafique,et al. Cross-architectural design space exploration tool for reconfigurable processors , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[32] Chris C. N. Chu,et al. FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[33] Reiner W. Hartenstein,et al. Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures , 2000, PATMOS.
[34] Cao Liang,et al. Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture , 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.
[35] Eric Horvitz,et al. Volunteering Versus Work for Pay: Incentives and Tradeoffs in Crowdsourcing , 2013, HCOMP.
[36] Natalie Parde,et al. Data-Driven Mapping Using Local Patterns , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[37] Henry Hoffmann,et al. Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[38] João M. P. Cardoso,et al. Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures , 2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006).
[39] Thomas W. Malone,et al. What makes things fun to learn? heuristics for designing instructional computer games , 1980, SIGSMALL '80.
[40] Yao-Wen Chang,et al. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[41] Alex K. Jones,et al. Interconnect customization for a hardware fabric , 2009, TODE.
[42] Anil Kumar Sistla,et al. UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies , 2013, TRETS.
[43] Rudy Lauwereins,et al. Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.
[44] Rajesh Gupta,et al. Network topology exploration of mesh-based coarse-grain reconfigurable architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[45] Jonathan Rose,et al. Trading quality for compile time: ultra-fast placement for FPGAs , 1999, FPGA '99.
[46] Jane Webster,et al. Making computer tasks at work more playful: Implications for systems analysts and designers , 1988, SIGCPR '88.
[47] Kingshuk Karuri,et al. A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[48] Patrick H. Madden,et al. Fast Analytic Placement using Minimum Cost Flow , 2007, 2007 Asia and South Pacific Design Automation Conference.
[49] Patrick H. Madden,et al. Recursive bisection placement: feng shui 5.0 implementation details , 2005, ISPD '05.
[50] Adrien Treuille,et al. Predicting protein structures with a multiplayer online game , 2010, Nature.
[51] Aviral Shrivastava,et al. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[52] Rabi N. Mahapatra,et al. A New Array Fabric for Coarse-Grained Reconfigurable Architecture , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.
[53] David Z. Pan,et al. DPlace2.0: A stable and efficient analytical placement based on diffusion , 2008, 2008 Asia and South Pacific Design Automation Conference.
[54] Carl Ebeling,et al. Architecture-adaptive routability-driven placement for FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[55] Kiyoung Choi,et al. Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture , 2010, ARC.
[56] Reiner W. Hartenstein,et al. A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[57] Seth Copen Goldstein,et al. PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.
[58] David S. Johnson,et al. Crossing Number is NP-Complete , 1983 .
[59] Michael Vitale,et al. The Wisdom of Crowds , 2015, Cell.
[60] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[61] Kiyoung Choi,et al. Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization , 2005, Design, Automation and Test in Europe.
[62] R. Hartenstein,et al. KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[63] Stephan W. Gehring,et al. Fast integrated tools for circuit design with FPGAs , 1998, FPGA '98.
[64] Anil Kumar Sistla,et al. Cross-Architectural Study of Custom Reconfigurable Devices Using Crowdsourcing , 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.
[65] Bjorn De Sutter,et al. Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array , 2008, HiPEAC.
[66] David Salesin,et al. The challenge of designing scientific discovery games , 2010, FDG.
[67] Martin Schader,et al. Managing the Crowd: Towards a Taxonomy of Crowdsourcing Processes , 2011, AMCIS.
[68] Manuel Blum,et al. Peekaboom: a game for locating objects in images , 2006, CHI.
[69] Georgi Gaydadjiev,et al. Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array , 2007, ARC.
[70] Reiner W. Hartenstein,et al. Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.
[71] George Theodoridis,et al. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools , 2007 .
[72] Benjamin B. Bederson,et al. Human computation: a survey and taxonomy of a growing field , 2011, CHI.
[73] Martin Margala,et al. A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
[74] Michalis D. Galanis,et al. Resource aware mapping on coarse grained reconfigurable arrays , 2009, Microprocess. Microsystems.