Atlas Level-1 Calorimeter Trigger System Architecture

The Level-1 Calorimeter Trigger is a fast pipelined system for the selection of rare physics processes in the ATLAS experiment at LHC. Its selectivity contributes to a rate reduction from the 40 MHz LHC bunch crossing rate down to the rst level accept rate of 75 kHz maximum. This is done by searching for isolated electrons and photons, hadrons, jets of particles and by calculating global energy sums in the calorimeter within the 2.0 s total latency of the level-1 trigger. Hence, fast hard-wired algorithms implemented in application-speciic integrated circuits (ASICs) and eld programmable gate arrays (FPGAs) are required. We present here a summary of the architecture of the ATLAS Level-1 Calorimeter Trigger and describe processor modules including printed circuit boards, Multi-Chip Modules, ASICs, FPGAs and their inter-connections.