Optimization of block-matching algorithms using custom instruction-based paradigm on NIOS II microprocessors

This paper focuses on the optimization of video coding standards motion estimation algorithms using Altera Custom Instructions based-paradigm and the combination of SDRAM with On-Chip memory in NIOS II processors. On one hand a complete algorithm profiling is achieved before the optimization, in order to find the code time leaks, afterward is developing a custom instruction set which will be added to the specific embedded design enhancing the original system. On the other hand, all possible permitted memories combinations between On-Chip memory and SDRAM have been tested for achieving the best performance combination. The final performance of the final design (memory optimization and custom instruction acceleration) is shown. This contribution, thus, outlines a low cost system, mapped on a Very Large Scale Integration (VLSI) technology which accelerates software algorithms by converting them to custom hardware logic block and shows the best combination between On-Chip memory and SDRAM for the NIOS II processor.