A power optimization method considering glitch reduction by gate sizing

We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 /spl mu/m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2% on average and by 63.4% maximum. This results in the reduction of total transitions by 12.8% on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4% on average and by 15.7% maximum further from the minimum-sized circuits.

[1]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[2]  Farid N. Najm,et al.  Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuitsy , 1995, 32nd Design Automation Conference.

[3]  Daniel Brand,et al.  Inaccuracies in power estimation during logic synthesis , 1996, ICCAD 1996.

[4]  Weitong Chuang,et al.  Power vs. delay in gate sizing: conflicting objectives? , 1995, ICCAD.

[5]  Y. Tamiya,et al.  Lp Based Cell Selection With Constraints Of Timing, Area, And Power Consumption , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[6]  Mary Jane Irwin,et al.  Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint , 1995, ISLPED '95.

[7]  Kurt Keutzer,et al.  On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, ICCAD.

[8]  Jochen A. G. Jess,et al.  Gate sizing in MOS digital circuits with linear programming , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[9]  Hidetoshi Onodera,et al.  An iterative gate sizing approach with accurate delay evaluation , 1995, ICCAD.

[10]  Mani Soma,et al.  Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[11]  How-Rern Lin,et al.  Power reduction by gate sizing with path-oriented slack calculation , 1995, ASP-DAC '95.