High-performance computing for systems of spiking neurons
暂无分享,去创建一个
[1] Steve Temple,et al. Sparse distributed memory using N-of-M codes , 2004, Neural Networks.
[2] Andrew D. Brown,et al. On-chip and inter-chip networks for modeling large-scale neural systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[3] A. Sloman. The Architecture of Brain and Mind Integrating Low-Level Neuronal Brain Processes with High-Level Cognitive Behaviours , in a Functioning Robot 2 , 2004 .
[4] William B. Toms,et al. Delay-insensitive, point-to-point interconnect using m-of-n codes , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[5] Eugene M. Izhikevich,et al. Which model to use for cortical spiking neurons? , 2004, IEEE Transactions on Neural Networks.
[6] Luis A. Plana,et al. The design and test of a smartcard chip using a CHAIN self-timed network-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[7] Stephen B. Furber,et al. Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.