Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks

Model checkers and sequential equivalence checkers have become essential tools for the semiconductor industry in recent years. The Hardware Model Checking Competition (HWMCC) was founded in 2006 with the purpose of intensifying research interest in these technologies, and establishing more of a science behind them. For example, the conference provided a standardized benchmark format, a challenging and diverse set of industrially-relevant public benchmarks, and as a consequence, a significant motivation for additional research to advance the state-of-the-art in solvers for these verification problems. This paper provides an analysis of the tools and benchmarks submitted to the 2014 Hardware Model Checking Competition.

[1]  K. Pearson.  VII. Note on regression and inheritance in the case of two parents , 1895, Proceedings of the Royal Society of London.

[2]  Gianpiero Cabodi,et al.  Thread-based multi-engine model checking for multicore platforms , 2013, TODE.

[3]  Dwayne Lee.  OpenSPARC - A Scalable Chip Multi-Threading Design , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[4]  Orna Grumberg,et al.  Lazy abstraction and SAT-based reachability in hardware model checking , 2012, 2012 Formal Methods in Computer-Aided Design (FMCAD).

[5]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.

[6]  Robert K. Brayton,et al.  Speculative reduction-based scalable redundancy identification , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Norbert Manthey.  Coprocessor 2.0 - A Flexible CNF Simplifier - (Tool Presentation) , 2012, SAT.

[8]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[9]  Ofer Strichman,et al.  Ultimately Incremental SAT , 2014, SAT.

[10]  Bernd Becker,et al.  Incremental preprocessing methods for use in BMC , 2011, Formal Methods Syst. Des..

[11]  Arie Gurfinkel,et al.  Interpolating Property Directed Reachability , 2014, CAV.

[12]  Lubos Brim,et al.  DiVinE - A Tool for Distributed Verification , 2006, CAV.

[13]  Armin Biere.  Yet another Local Search Solver and Lingeling and Friends Entering the SAT Competition 2014 , 2014 .

[14]  Koen Claessen,et al.  A liveness checking algorithm that counts , 2012, 2012 Formal Methods in Computer-Aided Design (FMCAD).

[15]  Orna Grumberg,et al.  Interpolation-sequence based model checking , 2009, 2009 Formal Methods in Computer-Aided Design.

[16]  Niklas Sörensson,et al.  Temporal induction by incremental SAT solving , 2003, BMC@CAV.

[17]  Anna Philippou,et al.  Tools and Algorithms for the Construction and Analysis of Systems , 2018, Lecture Notes in Computer Science.

[18]  Orna Grumberg,et al.  Intertwined Forward-Backward Reachability Analysis Using Interpolants , 2013, TACAS.

[19]  Alexander Nadel,et al.  Efficient SAT Solving under Assumptions , 2012, SAT.

[20]  Radek Pelánek,et al.  BEEM: Benchmarks for Explicit Model Checkers , 2007, SPIN.

[21]  Aaron R. Bradley,et al.  SAT-Based Model Checking without Unrolling , 2011, VMCAI.

[22]  Chung-Yang Huang,et al.  Adaptive interpolation-based model checking , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[23]  Yan Zhang,et al.  An incremental approach to model checking progress properties , 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

[24]  Martin Suda,et al.  Resolution-based methods for linear temporal reasoning , 2015 .

[25]  Viktor Schuppan,et al.  Linear Encodings of Bounded LTL Model Checking , 2006, Log. Methods Comput. Sci..

[26]  Fabio Somenzi,et al.  Better generalization in IC3 , 2013, 2013 Formal Methods in Computer-Aided Design.

[27]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[28]  Arie Gurfinkel,et al.  DRUPing for Interpolants , 2014 .

[29]  Armin Biere.  The AIGER And-Inverter Graph (AIG) Format Version 20070427 , 2007 .

[30]  Stefano Quer.  Model checking evaluation of airplane landing trajectories , 2013, International Journal on Software Tools for Technology Transfer.

[31]  Viktor Schuppan,et al.  Liveness Checking as Safety Checking , 2002, FMICS.

[32]  C. A. J. van Eijk,et al.  Sequential Equivalence Checking Based on Structural Similarities , 2000 .

[33]  Supratik Chakraborty,et al.  Efficient Guided Symbolic Reachability Using Reachability Expressions , 2006, TACAS.

[34]  Robert K. Brayton,et al.  GLA: Gate-level abstraction revisited , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[35]  Ofer Strichman,et al.  Preprocessing in Incremental SAT , 2012, SAT.

[36]  Arie Gurfinkel,et al.  DRUPing for interpolates , 2014, 2014 Formal Methods in Computer-Aided Design (FMCAD).

[37]  Robert K. Brayton,et al.  Efficient implementation of property directed reachability , 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

[38]  Gianpiero Cabodi,et al.  Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking , 2014, 2014 Formal Methods in Computer-Aided Design (FMCAD).

[39]  Armin Biere,et al.  Effective Preprocessing in SAT Through Variable and Clause Elimination , 2005, SAT.

[40]  Supratik Chakraborty,et al.  Efficient guided symbolic reachability using reachability expressions , 2007, International Journal on Software Tools for Technology Transfer.

[41]  PRASHANT AGGARWAL,et al.  End-to-End Formal using Abstractions to Maximize Coverage ( Invited Tutorial ) , 2011 .

[42]  Chao Wang,et al.  Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[43]  Christoph Weidenbach,et al.  Labelled Superposition for PLTL , 2012, LPAR.

[44]  Timo Latvala,et al.  Incremental and Complete Bounded Model Checking for Full PLTL , 2005, CAV.

[45]  Marijn J. H. Heule,et al.  Verifying Refutations with Extended Resolution , 2013, CADE.

[46]  Vigyan Singhal,et al.  Using Coverage to Deploy Formal Verification in a Simulation World , 2011, CAV.

[47]  Marijn Heule,et al.  Validating Unsatisfiability Results of Clause Sharing Parallel SAT Solvers , 2014, POS@SAT.

[48]  Marco Roveri,et al.  The nuXmv Symbolic Model Checker , 2014, CAV.

[49]  Armin Biere,et al.  Simple Bounded LTL Model Checking , 2004, FMCAD.

[50]  Gianpiero Cabodi,et al.  Automated abstraction by incremental refinement in interpolant-based model checking , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[51]  Chi-An Wu,et al.  A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[52]  Christoph Weidenbach,et al.  A PLTL-Prover Based on Labelled Superposition with Partial Model Guidance , 2012, IJCAR.

[53]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[54]  Jason Baumgartner,et al.  Scalable Automated Verification via Expert-System Guided Transformations , 2004, FMCAD.

[55]  Jason Baumgartner,et al.  Transformation-Based Verification Using Generalized Retiming , 2001, CAV.