An Adaptive Software-Based Deadlock Recovery Technique

Deadlock management has a direct effect on making a reliable connection between processing nodes in parallel computers. Networks using wormhole switching are the most vulnerable networks to deadlock occurrence due to chained blocking nature of this switching method. Different hardware based techniques for deadlock recovery were proposed in the literature which have considerable design complexity, while deadlock occurrence in a network is rare. A software based technique can reduce this cost while preserving performance. The only software based technique proposed in the literature is static and independent of network workload and working conditions. In this paper we present an adaptive software based technique for deadlock recovery, and validate its performance in the presence of different traffic patterns including uniform, hot spot, local and first matrix transpose (FMT) patterns in 8-ary 3-cube network (torus). Simulation results exhibit about 21% 20% 98% and 20% performance improvement under local, FMT, hotspot and uniform traffic patterns, respectively.

[1]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[2]  Timothy Mark Pinkston,et al.  On Deadlocks in Interconnection Networks , 1997, ISCA.

[3]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[4]  Yervant Zorian.  D&T Expands , 1999, IEEE Des. Test Comput..

[5]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[7]  Alain Greiner,et al.  SPIN: a scalable, packet switched, on-chip micro-network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[8]  Dara Rahmati,et al.  A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips , 2006, 2006 International Conference on Computer Design.

[9]  Pedro López,et al.  Software-based deadlock recovery technique for true fully adaptive routing in wormhole networks , 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).

[10]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[11]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[12]  K. Anjan,et al.  An efficient, fully adaptive deadlock recovery scheme: DISHA , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[13]  Jae H. Kim,et al.  Compressionless Routing: a framework for adaptive and fault-tolerant routing , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[14]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[15]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[16]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[17]  José Duato.  Improving the Efficiency of Virtual Channels with Time-Dependent Selection Functions , 1992, PARLE.

[18]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.