A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.

[1]  Bosco Leung,et al.  High-order single-stage single-bit oversampling A/D converter stabilized with local feedback loops , 1994 .

[2]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[3]  Un-Ku Moon,et al.  Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection , 2000 .

[4]  B. Leung,et al.  A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops , 1997 .

[5]  Baher S. Haroun,et al.  18.1 A 1.5V 2.4/2.9mW 79/50dB DR Σ∆ Modulator for GSM/WCDMA in a 0.13µm Digital Process , 2002 .

[6]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[7]  L. R. Carley,et al.  A noise-shaping coder topology for 15+ bit converters , 1989 .

[8]  Gabor C. Temes,et al.  A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements , 1993 .

[9]  T. Burger,et al.  A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[10]  James C. Candy,et al.  A Use of Double Integration in Sigma Delta Modulation , 1985, IEEE Trans. Commun..

[11]  Gert Cauwenberghs,et al.  Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration , 2000 .

[12]  I. Fujimori,et al.  A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range , 1997 .

[13]  B. Leung,et al.  Multibit Sigma - Delta A/D converter incorporating a novel class of dynamic element matching techniques , 1992 .

[14]  Thomas Burger,et al.  A 13.5mW, 185 MSample/s ΔΣ-modulator for UMTS/GSM dual-standard IF reception , 2001 .

[15]  Bernhard E. Boser,et al.  The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters , 2004 .