Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).

[1]  Mohab Anis,et al.  FPGA Design for Timing Yield Under Process Variations , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[3]  Subhasish Mitra,et al.  Robust System Design to Overcome CMOS Reliability Challenges , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[4]  Qiang Xu,et al.  Fine-grained characterization of process variation in FPGAs , 2010, 2010 International Conference on Field-Programmable Technology.

[5]  Yu Cao,et al.  The Impact of NBTI on the Performance of Combinational and Sequential Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  John P. Hayes,et al.  On-line sensing for healthier FPGA systems , 2010, FPGA '10.

[7]  Sachin S. Sapatnekar,et al.  Adaptive techniques for overcoming performance degradation due to aging in digital circuits , 2009, 2009 Asia and South Pacific Design Automation Conference.

[8]  Narayanan Vijaykrishnan,et al.  Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[9]  Zhenyu Qi,et al.  Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay , 2009, 2009 10th International Symposium on Quality Electronic Design.

[10]  I. C. Teixeira,et al.  Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects , 2011, 2011 12th Latin American Test Workshop (LATW).

[11]  Narayanan Vijaykrishnan,et al.  FLAW: FPGA lifetime awareness , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  Farid N. Najm,et al.  An adaptive FPGA architecture with process variation compensation and reduced leakage , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Wayne Luk,et al.  Dynamic voltage scaling for commercial FPGAs , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[14]  João Paulo Teixeira,et al.  Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance , 2010, J. Low Power Electron..

[15]  C. Leong,et al.  Design and test issues of a FPGA based data acquisition system for medical imaging using PEM , 2005, 14th IEEE-NPSS Real Time Conference, 2005..

[16]  Narayanan Vijaykrishnan,et al.  Toward Increasing FPGA Lifetime , 2008, IEEE Transactions on Dependable and Secure Computing.

[17]  João Paulo Teixeira,et al.  Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors , 2011, 29th VLSI Test Symposium.

[18]  João Paulo Teixeira,et al.  Low-sensitivity to process variations aging sensor for automotive safety-critical applications , 2010, 2010 28th VLSI Test Symposium (VTS).

[19]  C. Leong,et al.  Design and test issues of an FPGA based data acquisition system for medical imaging using PEM , 2006, IEEE Transactions on Nuclear Science.