Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shaping capability and reduced dynamic range. This paper demonstrates how to perform more advanced EF MES for various types of data converters. Moreover, this paper also proposes the use of digital prediction to address the dynamic range loss issue.

[1]  Van De Plassche,et al.  Dynamic element matching for high-accuracy monolithic D/A converters , 1976, 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Nan Sun,et al.  Predicting ADC: A new approach for low power ADC design , 2014, 2014 IEEE Dallas Circuits and Systems Conference (DCAS).

[3]  Nan Sun,et al.  Second-order DAC MES for SAR ADCs , 2017 .

[4]  Ian Galton Spectral shaping of circuit errors in digital-to-analog converters , 1997 .

[5]  Kok Lim Chan,et al.  A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[6]  Nan Sun High-Order Mismatch-Shaped Segmented Multibit ΔΣ DACs With Arbitrary Unit Weights. , 2012 .

[7]  Ian Galton,et al.  Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters , 2001 .

[8]  R. T. Baird,et al.  A low oversampling ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC , 1996 .

[9]  Akira Matsuzawa,et al.  A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[10]  Ian Galton Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .

[11]  Nan Sun,et al.  Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.

[13]  Nan Sun,et al.  A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[14]  Akira Matsuzawa,et al.  A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[15]  H. Jonathan Chao,et al.  A signal-specific approach for reducing SAR-ADC power consumption , 2013, 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[16]  Nan Sun,et al.  A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[17]  Nan Sun,et al.  Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit $\Delta\Sigma$ Modulators , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[18]  I. Fujimori,et al.  A 90 dB SNR, 2.5 MHz output rate ADC using cascaded multibit /spl Delta//spl Sigma/ modulation at 8x oversampling ratio , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[19]  Koji Obata,et al.  A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[20]  Nan Sun,et al.  Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit $\Delta\Sigma$ ADCs , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[22]  Gabor C. Temes,et al.  A Segmented Data-Weighted-Averaging Technique , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[23]  R. Schreier,et al.  Noise-shaped multbit D/A convertor employing unit elements , 1995 .

[24]  K. Nguyen,et al.  A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[25]  Tai-Haur Kuo,et al.  Advancing Data Weighted Averaging Technique for Multi-Bit Sigma–Delta Modulators , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  Kok Lim Chan,et al.  Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Nan Sun,et al.  A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators , 2017, 2017 Symposium on VLSI Circuits.

[28]  Tien-Yu Lo,et al.  An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS , 2016, IEEE Journal of Solid-State Circuits.

[29]  Michael P. Flynn,et al.  A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC , 2012, IEEE Journal of Solid-State Circuits.

[30]  Nan Sun,et al.  Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[31]  B. Leung,et al.  Multibit Sigma - Delta A/D converter incorporating a novel class of dynamic element matching techniques , 1992 .

[32]  Terri S. Fiez,et al.  A Low Oversampling Ratio 14b 500-kHz ADC with a Self-Calibrated Multibit DAC , 1996 .

[33]  Ian Galton,et al.  The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[34]  Kok Lim Chan,et al.  Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs , 2008, IEEE Journal of Solid-State Circuits.

[35]  Nan Sun High-Order Mismatch-Shaping in Multibit DACs , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[36]  Gabor C. Temes,et al.  Switched-capacitor DAC with analogue mismatch correction , 1999 .