Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs
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[1] Jonathan Rose,et al. Design, layout and verification of an FPGA using automated tools , 2005, FPGA '05.
[2] Fatih Kocan,et al. Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays , 2004, FPL.
[3] Vaughn Betz,et al. How Much Logic Should Go in an FPGA Logic Block? , 1998, IEEE Des. Test Comput..
[4] Steven J. E. Wilton,et al. A detailed power model for field-programmable gate arrays , 2005, TODE.
[5] Carl Sechen,et al. Efficient canonical form for boolean matching of complex functions in large libraries , 2001, ICCAD 2001.
[6] Christof Paar,et al. An FPGA implementation and performance evaluation of the Serpent block cipher , 2000, FPGA '00.
[7] Altera. Apex ii programmable logic device family data sheet , 2002 .
[8] Malgorzata Marek-Sadowska,et al. Universal logic gate for FPGA design , 1994, ICCAD '94.
[9] Carl Ebeling,et al. The Triptych FPGA architecture , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[10] Stephen Dean Brown,et al. Hybrid FPGA Architecture , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[11] Guy Lemieux,et al. Using sparse crossbars within LUT , 2001, FPGA '01.
[12] Oliver Diessel,et al. On the placement and granularity of FPGA configurations , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).
[13] Narayanan Vijaykrishnan,et al. Improving soft-error tolerance of FPGA configuration bits , 2004, ICCAD 2004.
[14] John Wawrzynek,et al. Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[15] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[16] V. Kamakoti,et al. A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).
[17] Martin D. F. Wong,et al. On Designing ULM-Based FPGA Logic Modules , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.
[18] Wayne Wolf,et al. FPGA-Based System Design , 2004 .
[19] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .
[20] Bai Nguyen,et al. An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions , 1999, FPGA.
[21] Jason Cong,et al. RASP: A General Logic Synthesis System for SRAM-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[22] Jonathan Rose,et al. The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .
[23] Tsutomu Sasao,et al. Switching Theory for Logic Synthesis , 1999, Springer US.
[24] Reiner W. Hartenstein,et al. A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[25] Scott Hauck,et al. Reconfigurable computing: a survey of systems and software , 2002, CSUR.
[26] Wai Keung Wong,et al. FPGA implementation of a microcoded elliptic curve cryptographic processor , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).
[27] Takashi Horiyama,et al. Folding of logic functions and its application to look up table compaction , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..
[28] David Lewis,et al. Using Sparse Crossbars within LUT Clusters , 2001 .