Design of Low Power Digital Clock on FPGA using Different IO Standards

Objective: This paper analyzes the power of a digital clock with the help of Xilinx ISE V-14.2 and executing it on virtex-6 FPGA and Spartan 3E FPGA. Methods: On FPGA we use Verilog HDL to synthesize the clock where the targeted device is FPGA. Analysis of different IO Standard on Xilinx software depicts the least power consumption for 2 different frequencies. Findings: With the results portrayed in the paper we get a combination of perfect low power consuming IC design. Xilinx XPower analyzer has been used to analyze the power consumption of digital clock based on FPGA. Further power utilization using different IO standards at different frequency has been decreased effectively. The device when operating at 50 Mega Hertz and 100 Mega Hertz frequency the reduction of power is attained. Application: This low power consuming IC design will be useful wherever digital clock is used and energy efficiency is to be attained.