9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping

Noise-shaping (NS) SAR ADCs using passive loop filters have drawn increasing attention due to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution (ENOB≤13b) due to two main challenges. The 1st one is thermal noise. Passive loop filters cannot provide gain [1]. Hence, their suppression of the comparator noise is limited. In addition, every capacitor switching introduces extra kT/C noise. To reduce noise, a passive gain of 2 is realized in [2]. It also realizes passive voltage summation, which obviates the need for a multipath comparator, further reducing the comparator noise. Nevertheless, it uses small capacitors for residue sampling to minimize signal attenuation, leading to a large total kT/C noise of 20kT/C (C is the DAC size). Also, its NTF is mild (zero at 0.5), leading to limited SQNR benefit. The 2nd challenge is DAC mismatch. Classic DEM is unsuitable for SARs with a high-resolution DAC due to excessive hardware cost. To reduce circuit complexity, Ref. [3] applies DEM only to the MSB part of the DAC, but the LSB part still produces considerable errors. The mismatch error shaping (MES) technique of [4] is well suited for high-resolution binary DACs due to low hardware complexity, but it has its own limitations. First, it can only achieve 1st-order shaping with limited error suppression capability. Also, being 1st-order, it has strong signal dependence and can produce considerable tones, especially at low input amplitudes. In addition, it suffers from signal range loss.

[1]  Nan Sun,et al.  A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators , 2017, 2017 Symposium on VLSI Circuits.

[2]  Nan Sun,et al.  Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Tien-Yu Lo,et al.  27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Chun-Cheng Liu,et al.  28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[5]  Ying-Zu Lin,et al.  20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).