Chip-packaging interaction: a critical concern for Cu/low k packaging

Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we will first review the experimental techniques for package thermal deformation measurement and interfacial fracture energy measurement for low k interfaces. Then 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution Moire interferometry is employed to examine the packaging effect on low k interconnect reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Possible solutions and future study are discussed.

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