Physically based description of quasi-saturation region of vertical DMOS power transistors

For short circuit design protection, quasi-saturation behaviour of vertical power DMOS transistors has to be included in circuit simulator compact models. In this region an unexpected increase in current has been observed, due to the injection of electrons from the n/sup +/ source region into the n-substrate. The purpose of this paper is to analyze this effect and include its results in a compact model for circuit simulation.