Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited)

We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for future technology generations. Resistance becomes the dominant contribution for timing for local wires at 65 nm and beyond, a major qualitative change. For scaled wires, maintaining global wire routes within 1 clock period is expensive in terms of power consumption. An acceptable solution involves reverse scaling of global wires leading to RLC transmission line behavior which results in significant power savings. RLC transmission for scaled signal wires is otherwise negligible.

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