Thin hardmask patterning stacks for the 22-nm node

This paper presents robust trilayer lithography technology for cutting-edge IC fabrication and double-patterning applications. The goal is to reduce the thickness of a silicon hardmask so that the minimum thickness of the photoresist is not limited by the etch budget and can be optimized for lithography performance. Successful results of pattern etching through a 300-nm carbon layer are presented to prove that a 13.5-nm silicon hardmask is thick enough to transfer the line pattern. Another highlight of this work is the use of a simulation tool to design the stack so that UV light is concentrated at the bottom of the trenches. This design helps to clear the resist in the trenches and prevent resist top loss. An experiment was designed to validate the assumption with 45-nm dense lines at various exposure doses, using an Exitech MS-193i immersion microstepper (NA = 1.3) at the SEMATECH Resist Test Center. Results show that such a stack design obtains very wide CD processing window and is robust for 1:3 line patterning at the diffraction limit, as well as for patterning small contact holes.