Design and implementation of Carry Select Adder without using multiplexers

High performance digital adder with reduced area and low power consumption is an important design constraint for advanced processors. The speed of operation of such an adder is limited by carry propagation from input to output. Our work is based on designing an optimized adder for advanced processors. This paper discusses about the implementation of Carry Select Adder without using MUX for final selection. Our approach uses first, the implementation of cin=0 adder and then Excess 1 adder. Excess 1 adder is designed in such a way that it becomes a first zero finding logic and replaces the final MUX stage used in traditional approach. Parallel adder configuration is also used to reduce the delay between stages. Removing the MUX stage will reduce the area as well as propagation delay to give much higher performance for the adder. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. The adder is implemented on Spartan 3E FPGA and is compared with CSA with MUX, Kogge Stone adder and FPGA adder. Results show that the new adder gives reduced area and better speed compared to other adders.

[1]  Magdy Bayoumi,et al.  A low power and reduced area carry select adder , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[2]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[3]  Mircea R. Stan,et al.  A unified design space for regular parallel prefix adders , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  A.J. Al-Khalili,et al.  Performance of Parallel Prefix Adders implemented with FPGA technology , 2007, 2007 IEEE Northeast Workshop on Circuits and Systems.

[5]  Orest J. Bedrij.  Carry-Select Adder , 1962, IRE Trans. Electron. Comput..

[6]  Massoud Pedram,et al.  Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders , 2005, Sixth international symposium on quality electronic design (isqed'05).

[7]  Otmane Aït Mohamed,et al.  A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[8]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[9]  D. Mlynek,et al.  A New Architecture for an Automatic Generation of Fast Pipelined Adders , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[10]  B. Ramkumar,et al.  Low-Power and Area-Efficient Carry Select Adder , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  U SajeshKumar,et al.  Efficient Carry Select Adder Design for FPGA Implementation , 2012 .

[12]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[13]  Lee-Sup Kim,et al.  A low power carry select adder with reduced area , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[14]  Neil Burgess,et al.  A GaAs 32-bit adder , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[15]  Massimo Alioto,et al.  A gate-level strategy to design Carry Select Adders , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[16]  Sanjeev Saxena,et al.  On Parallel Prefix Computation , 1994, Parallel Process. Lett..

[17]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[18]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..