A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup

In the last years FPGAs have become very important for electronic designs - they are very flexible, provide high configurability and allow short turn around times. Especially for rapid prototyping (RP) another feature plays an important rule: the nearly infinite reprogrammability. However, handling these devices in the engineering process is not an easy issue. Therefore our approach presents an efficient, flexible and versatile FPGA configuration methodology based on partial bitstream merging at design time

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