Faults, error bounds and reliability of nanoelectronic circuits

This paper is concerned with faults, error bounds and reliability modeling of nanotechnology-based circuits. First, we briefly review failure mechanisms and fault models in nanoelectronics. Second, reliability functions based on probabilistic models are developed for unreliable logic gates. We then show that fundamental gate error bounds for general probabilistic computation can be derived using the nonlinear mapping functions constructed from the gate models. Finally, an analytical approach is proposed for estimating reliabilities of nanoelectronic circuits. This approach is based on the probabilistic modeling of unreliable logic gates and interconnects. In spite of the approximations used in probabilistic modeling, our study suggests that the proposed approach provides a simple and efficient way to model the reliability of nanoelectronic circuits.

[1]  P. D. Tougaw,et al.  A device architecture for computing with quantum dots , 1997, Proc. IEEE.

[2]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[3]  Fabrizio Lombardi,et al.  Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models , 2000, Records of the IEEE International Workshop on Memory Technology, Design and Testing.

[4]  Jie Han.  Fault-tolerant architectures for nanoelectronic and quantum devices , 2004 .

[5]  Sandeep K. Shukla,et al.  Tools and techniques for evaluating reliability trade-offs for NANO-architectures , 2004 .

[6]  Jeong-Taek Kong,et al.  CAD for nanometer silicon design challenges and success , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Paul S. Ho,et al.  Electromigration reliability issues in dual-damascene Cu interconnections , 2002, IEEE Trans. Reliab..

[8]  Mehdi Baradaran Tahoori,et al.  Defects and faults in quantum cellular automata at nano scale , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[9]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[10]  Seth Copen Goldstein,et al.  Molecular electronics: from devices and interconnect to circuits and architecture , 2003, Proc. IEEE.

[11]  Jürgen Alt,et al.  Simulation of non-classical faults on the gate level-fault modeling , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[12]  Robert S. Swarz,et al.  Reliable Computer Systems: Design and Evaluation , 1992 .

[13]  Jie Han,et al.  A system architecture solution for unreliable nanoelectronic devices , 2002 .

[14]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[15]  J.A.B. Fortes,et al.  Bifurcations and fundamental error bounds for fault-tolerant computations , 2005, IEEE Transactions on Nanotechnology.

[16]  J.A. Abraham,et al.  Fault and error models for VLSI , 1986, Proceedings of the IEEE.

[17]  R. I. Bahar,et al.  Nano, Quantum and Molecular Computing , 2004, Springer US.

[18]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[19]  Jie Chen,et al.  A probabilistic-based design for nanoscale computation , 2004 .

[20]  Prithviraj Banerjee,et al.  Fault tolerant VLSI systems , 1993 .

[21]  Anurag Mittal,et al.  Nano-CMOS Circuit and Physical Design , 2004 .

[22]  Sandeep K. Shukla,et al.  Nano, quantum and molecular computing: implications to high level design and validation , 2004 .