A performance evaluation of a 3-stage ATM Clos switch under bursty traffic

Performance of ATM networks will depend on switch performance and architectures. The main problem when designing a switch is due to the fact that the future traffic is unknown. Traffics are expected to be bursty. Input processes into one switch are not mostly source processes (voice, data or video traffic), they are mostly output processes from other switches. So when studying a switch performance, it is necessary to verify whether the assumptions on input processes still hold for output processes. Performance of an ATM switch based on a three-stage Clos Network with output buffers is studied under "Bursty Geometric" arrivals. The aim of the analysis is to dimension the output buffers of each of the three stages of the considered A TM switch. The output traffic is studied. It is well approximated by a bursty geometric process. The interstage traffic and the output traffic of the switch can consequently be approximated by such processes. It validates the input assumptions. An approximate model of the switch is presented. Discrete event simulations are used to validate our model. Analysis of the results shows that the switch dimensioning is important. The use of non-symmetric switching elements reveals itself efficient for bursty traffic. The burstiness has an influence on the cell loss probability but it has no influence on the cell delay and no influence on the best memory repartition for a given global memory size and a given architecture.