Scalable, high-quality, SAT-based multi-layer escape routing

Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunately, multi-layer escape routing is much more challenging than single-layer escape routing, and currently lacks scalable, high-quality, automatic solutions. As a result, multi-layer escape routing for high-end BGAs typically requires extensive human intervention in practice.

[1]  Richard M. Karp,et al.  Global wire routing in two-dimensional arrays , 1987, 24th Annual Symposium on Foundations of Computer Science (sfcs 1983).

[2]  MATTHIAS MIDDENDORF,et al.  On the complexity of the disjoint paths problem , 1993, Comb..

[3]  J. Darnauer,et al.  PLANAR INTERCHANGEABLE 2-TERMINAL ROUTING , 1995 .

[4]  Wayne Wei-Ming Dai,et al.  Pin assignment and routing on a single-layer Pin Grid Array , 1995, ASP-DAC '95.

[5]  Wayne Wei-Ming Dai,et al.  Single-layer fanout routing and routability analysis for Ball Grid Arrays , 1995, ICCAD.

[6]  Jens Vygen,et al.  NP-completeness of Some Edge-disjoint Paths Problems , 1995, Discret. Appl. Math..

[7]  Leonidas Palios Connecting the Maximum Number of Nodes in the Grid to the Boundary with Nonintersecting Line Segments , 1997, J. Algorithms.

[8]  Dongsheng Wang,et al.  A performance-driven I/O pin routing algorithm , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[9]  Y. Takeuchi,et al.  Escape routing design to reduce the number of layers in area array packaging , 2000 .

[10]  Francis Y. L. Chin,et al.  Escaping a Grid by Edge-Disjoint Paths , 2000, SODA '00.

[11]  Martin D. F. Wong,et al.  Wire Routing and Satisfiability Planning , 2000, Computational Logic.

[12]  Miroslaw Truszczynski,et al.  More on Wire Routing with ASP , 2001, Answer Set Programming.

[13]  Shaodi Gao,et al.  An efficient ball grid array router , 2002 .

[14]  Huntsville,et al.  IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION , 2003 .

[15]  Martin D. F. Wong,et al.  Rectilinear Steiner Tree Construction Using Answer Set Programming , 2004, ICLP.

[16]  Atsushi Takahashi,et al.  A global routing method for 2-layer ball grid array packages , 2005, ISPD '05.

[17]  Yao-Wen Chang,et al.  A routing algorithm for flip-chip design , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[18]  Rui Shi,et al.  Efficient escape routing for hexagonal array of high density I/Os , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[19]  Atsushi Takahashi,et al.  Monotonic parallel and orthogonal routing for single-layer ball grid array packages , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[20]  Rui Shi,et al.  Layer Minimization of Escape Routing in Area Array Packaging , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[21]  Optimal bus sequencing for escape routing in dense PCBs , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[22]  Yao-Wen Chang,et al.  A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Esra Erdem,et al.  Comparing ASP, CP, ILP on two challenging applications: wire routing and haplotype inference , 2008 .

[24]  Nikolaj Bjørner,et al.  Z3: An Efficient SMT Solver , 2008, TACAS.

[25]  Martin D. F. Wong,et al.  Ordered escape routing based on Boolean satisfiability , 2008, 2008 Asia and South Pacific Design Automation Conference.

[26]  Yao-Wen Chang,et al.  Multi-layer global routing considering via and wire capacities , 2008, ICCAD 2008.

[27]  Tan Yan,et al.  A correct network flow model for escape routing , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[28]  Yao-Wen Chang,et al.  An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Hui Kong,et al.  Optimal layer assignment for escape routing of buses , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[30]  Martin D. F. Wong,et al.  On the escape routing of differential pairs , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[31]  Martin D. F. Wong,et al.  Recent research development in PCB layout , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[32]  Hui Kong,et al.  Optimal simultaneous pin assignment and escape routing for dense PCBs , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[33]  Laurent Perron,et al.  Operations Research and Constraint Programming at Google , 2011, CP.

[34]  Evangeline F. Y. Young,et al.  A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[35]  Yao-Wen Chang,et al.  Escape routing for staggered-pin-array PCBs , 2011, ICCAD 2011.

[36]  Tai-Chen Chen,et al.  Escape routing of differential pairs considering length matching , 2012, 17th Asia and South Pacific Design Automation Conference.

[37]  Yao-Wen Chang,et al.  Layer minimization in escape routing for staggered-pin-array PCBs , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[38]  Alexander Nadel,et al.  Finding Bounded Path in Graph Using SMT for Automatic Clock Routing , 2015, CAV.

[39]  Alan J. Hu,et al.  SAT Modulo Monotonic Theories , 2014, AAAI.

[40]  Seong-I Lei,et al.  Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.