High performance digital circuitry for Gigabit PON-networks

Mixed mode chip design flow The adopted design flow shows following highlights : Synthesis is started early in the flow, to have fast knowledge of timing closure problems (both after synthesis and after P&R). Early estimation of power consumption helps to effectively locate big power spenders / crosstalk generators. Analog blocks are modeled in many operating conditions. This allows fast and automatic Static Timing Analysis at chip level for finding timing problems at analog/digital interfaces, instead of long and inefficient mixed-mode simulations.