A 64K by l b DRAM with multiplexed address inputs, packaged in a standard 300-mil wide 16 pin DIP, but with only one address strobe clock (RAS), will be reported. After one row address is selected with the RAS clock, as in normal multiplexed devices, column address selection (one of the 2561, boundarylrow) can be performed in a manner similar to static memory: data from the output changes in accordance with the change of column address without an address strobe clock. Access time from the columnzdress, and cycle time are typically 3511s. The deaffords CS (Chip select) instead of column address strobe (CAS), enabling or disabling the output at high speed. Typical chip select access time is less than 12ns. In write operation the falling edge of write enable (WE) latches the column address and Data In, and the write operation period extends automatically to the time when the device indicates the completion of writing; write time out. Following read or write operation starts immediately according to the state of WE. Figure 1 illustrates the concept of static column operation. The storage cells, sense amplifiers, and row decoders are almost the same as those of current 64K DRAMS. The sense amplifiers are fully dynamic with active pull up circuits. Word lines are pushed above Vcc to utilize the full charge of cells.