A parallel processing architecture for parameter estimation with recursive least squares

The recursive least-squares method (RLS) is often employed in the identification of the linear discrete-time system, in which the parameters are time-varying. This paper aims at producing the output which is an estimation of the system parameters, and derives a new algorithm which minimizes the RLS criterion with (time-variable) forgetting factor. A parallel architecture is proposed which executes the algorithm. the derived algorithm is composed of two-step processes, which are the Agee-Turner PD factorization update theorem and the forward-substitution for solving linear triangular systems. the proposed parallel architecture is composed of a large number of processing elements (PE) connected in a regular way. the communication is performed only between adjacent PE, and the architecture can easily be implemented by VLSI. It can be considered as a systolic array composed of PE with a queue (FIFO memory). By introducing PE with a queue, the two-step processes can be executed in parallel for the first time. It is shown that by employing the proposed parallel architecture composed of (N2 + 5N − 2)/2 PE in the real-time processing, the estimated parameters for any time can be produced as the output, in a processing time independent of the number of parameters of the estimation, even though the computational complexity is of the order of square of the number of estimated parameters.