A 3.5 ns, 64 bit, carry-lookahead adder

A 3.5 ns, 64 bit, carry-lookahead adder has been designed in full-custom domino logic and manufactured in a standard 1 /spl mu/m CMOS technology featuring two metal levels. The adder has a novel array structure which represents a variant of the architecture suggested by Brent and Kung. As opposed to the latter, however, it does not require the back propagation of the signals which is necessary for the intermediate carry bits; hence only log/sub 2/ n logic levels are employed for the generation of all the carry signals. Furthermore, the structure is highly regular and modular and can be assembled with n log/sub 2/ n identical cells with a fan-out of 2. Therefore, a compact circuit is achieved with excellent performance. The occupied area is 3370/spl times/482 /spl mu/m/sup 2/ with a worst-case 650 mW power dissipation at 100 MHz.

[1]  Ralph K. Cavin,et al.  A 250-MHz wave pipelined adder in 2-/spl mu/m CMOS , 1994 .

[2]  C. Svensson,et al.  Impact of clock slope on true single phase clocked (TSPC) CMOS circuits , 1994, IEEE J. Solid State Circuits.

[3]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[4]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[5]  A. L. Fisher,et al.  Ultrafast compact 32-bit CMOS adders in multiple-output domino logic , 1989 .

[6]  Earl E. Swartzlander,et al.  A Spanning Tree Carry Lookahead Adder , 1992, IEEE Trans. Computers.

[7]  Burton M. Leary,et al.  A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[9]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[10]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[11]  Belle W. Y. Wei,et al.  Area-Time Optimal Adder Design , 1990, IEEE Trans. Computers.