Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms

This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed Implementation approach concludes higher system performance while reducing operating power consumption. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of 218MHz and a bandwidth of 664Mbits/s.

[1]  Nicolas Sklavos.  On the Hardware Implementation Cost of Crypto-Processors Architectures , 2010, Inf. Secur. J. A Glob. Perspect..

[2]  Rupali S. Balpande,et al.  Design of FPGA Based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor , 2011, 2011 International Conference on Communication Systems and Network Technologies.

[3]  P. Glenn Gulak,et al.  An area-efficient universal cryptography processor for smart cards , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  장훈,et al.  [서평]「Computer Organization and Design, The Hardware/Software Interface」 , 1997 .

[5]  M. Zulkifli,et al.  Reduced stall MIPS architecture using pre-fetching accelerator , 2009, 2009 International Conference on Electrical Engineering and Informatics.

[6]  Karthi Balasubramanian,et al.  Low-power pipelined MIPS processor design , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

[7]  Zainalabedin Navabi.  VHDL: Modular Design and Synthesis of Cores and Systems, 3rd Edition , 2007 .

[8]  PRAVIN B. GHEWARI,et al.  Efficient Hardware Design and Implementation of AES Cryptosystem , 2010 .

[9]  Ali Afzali-Kusha,et al.  Dynamic Power Reduction of Stalls in Pipelined Architecture Processors , 2011 .

[10]  A. Neslin Ismailoglu,et al.  A high speed ASIC implementation of the Rijndael algorithm , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[11]  Enver Ever,et al.  Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

[12]  Tufan Egemen.  DESIGN AND SYSTEMC IMPLEMENTATION OF A CRYPTO PROCESSOR FOR AES AND DES ALGORITHMS , 2007 .

[13]  Mohamed Khalil Hani,et al.  DESIGN AND IMPLEMENTATION OF A PRIVATE AND PUBLIC KEY CRYPTO PROCESSOR FOR NEXT-GENERATION IT SECURITY APPLICATIONS , 2006 .