Towards an MPEG-4 HW/SW integrated solution: an efficient SIMD architecture for exhaustive BMA

This paper presents an efficient SIMD architecture for exhaustive block matching algorithm (EBMA). This module is part of the MPEG-4 part 9: reference hardware description. The developed module is prototyped and synthesized for Xilinx Virtex II FPGA XC2V3000-4. The proposed module processes 30.75 CIF frame /sec using the max clock frequency. This module utilizes 12% of the register bits, 16% of the block RAMs, and 15% of the LUTs in Xilinx Virtex II FPGA XC2V3000-4

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