An online thermal-constrained task scheduler for 3D multi-core processors

Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints.

[1]  Riccardo Bettati,et al.  Reactive speed control in temperature-constrained real-time systems , 2006, 18th Euromicro Conference on Real-Time Systems (ECRTS'06).

[2]  Eun Jung Kim,et al.  Temperature-aware scheduler based on thermal behavior grouping in multicore systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Ding-Ming Kwai,et al.  Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization , 2011, 2011 Design, Automation & Test in Europe.

[5]  Yusuf Leblebici,et al.  Dynamic thermal management in 3D multicore architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Alpha 21264 / EV 6 Microprocessor Hardware Reference Manual , 2000 .

[7]  Sarma B. K. Vrudhula,et al.  Throughput optimal task allocation under thermal constraints for multi-core processors , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[8]  Luca Benini,et al.  Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization , 2008, 2008 Design, Automation and Test in Europe.

[9]  Muhannad S. Bakir,et al.  3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[10]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[11]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[12]  Yuan Xie,et al.  Design space exploration for 3D integrated circuits , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[13]  Narayanan Vijaykrishnan,et al.  Interconnect and thermal-aware floorplanning for 3D microprocessors , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[14]  Jun Yang,et al.  Thermal-Aware Task Scheduling for 3D Multicore Processors , 2010, IEEE Transactions on Parallel and Distributed Systems.

[15]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[16]  Tajana Simunic,et al.  Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Riccardo Bettati,et al.  Reactive Speed Control in Temperature-Constrained Real-Time Systems , 2006, ECRTS.

[18]  R. Viswanath Thermal Performance Challenges from Silicon to Systems , 2000 .

[19]  Jason Cong,et al.  Thermal via planning for 3-D ICs , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..