On the soft information extraction from hard-decision outputs in MLC NAND flash memory

In this work, we propose a scheme to extract soft information from hard-decision outputs in multi-level per cell (MLC) flash memory based on a cell-to-cell interference model. It will be shown that the soft information extracted in the form of log-likelihood ratio (LLR) by taking into account a dominant cell-to-cell interference term provides significant performance improvements when the error-control system is designed with an error-correcting code with iterative decoding algorithm, e.g. low-density parity-check (LDPC) code with the Belief-Propagation (BP) algorithm. To confirm the claims, we design error-control systems with a conventional Bose-Chaudhuri-Hocquenghem (BCH) code and an LDPC code with/without the soft information extraction. Performances of the systems are extensively evaluated and compared, which clearly shows that the soft information extraction based on the cell-to-cell interference model leads to a considerably better performance.

[1]  Jaejin Lee,et al.  Coupling canceller maximum-likelihood (CCML) detection for multi-level cell NAND flash memory , 2011, IEEE Transactions on Consumer Electronics.

[2]  T. Takeshima,et al.  A 98 mm/sup 2/ die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell , 1996 .

[3]  Yan Li,et al.  A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate , 2009, IEEE Journal of Solid-State Circuits.

[4]  Jaekyun Moon,et al.  Statistical Analysis of Flash Memory Read Data , 2011, 2011 IEEE Global Telecommunications Conference - GLOBECOM 2011.

[5]  Donghyuk Park,et al.  Floating-Gate Coupling Canceller for Multi-Level Cell NAND Flash , 2011, IEEE Transactions on Magnetics.

[6]  Dae-Seok Byeon,et al.  A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[7]  Tong Zhang,et al.  On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Ken Takeuchi,et al.  A multipage cell architecture for high-speed programming multilevel NAND flash memories , 1998, IEEE J. Solid State Circuits.

[9]  Jaekyun Moon,et al.  Statistical Characterization of Noise and Interference in NAND Flash Memory , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  K. Takeuchi,et al.  A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[11]  Ken Takeuchi,et al.  A Double-Leve1- V th Select Gate Array Architecture for Multilevel NAND Flash Memories , 1996 .

[12]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[13]  A. Inoue,et al.  A 70 nm 16 Gb 16-Level-Cell NAND flash Memory , 2008, IEEE Journal of Solid-State Circuits.

[14]  Tong Zhang,et al.  Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Jeongseok Ha,et al.  Concatenated BCH codes for NAND flash memories , 2012, 2012 IEEE International Conference on Communications (ICC).

[16]  Richard D. Wesel,et al.  Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization , 2011, 2011 IEEE Global Telecommunications Conference - GLOBECOM 2011.

[17]  Tong Zhang,et al.  Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.