Design for built-in FPGA reliability via fine-grained 2-D error correction codes
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[1] Alan Wood,et al. The impact of new technology on soft error rates , 2011, 2011 International Reliability Physics Symposium.
[2] Ehab Mohsen. Balancing Performance , Power , and Cost with Kintex-7 FPGAs , 2009 .
[3] Mark Anders,et al. Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.
[4] Mehdi Baradaran Tahoori,et al. Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[5] Mihalis Psarakis,et al. Combining checkpointing and scrubbing in FPGA-based real-time systems , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).
[6] R.C. Baumann,et al. Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.
[7] M. Lopez-Vallejo,et al. Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers , 2013, IEEE Transactions on Nuclear Science.
[8] Mehdi Baradaran Tahoori,et al. Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] F. Novak,et al. SEU Recovery Mechanism for SRAM-Based FPGAs , 2012, IEEE Transactions on Nuclear Science.
[10] M. Caffrey,et al. SEU Mitigation Techniques for Virtex FPGAs in Space Applications , 1999 .
[11] K. Chapman. SEU Strategies for Virtex-5 Devices , 2010 .