Impact of technology parameters on device performance of UTB-SOI CMOS

Abstract Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In this paper, we analyse the impact of different combinations of doping profiles and gate sidewall spacer thicknesses on device performance. For this purpose we have simulated fully depleted SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation.

[1]  Chenming Hu,et al.  An adjustable work function technology using Mo gate for CMOS devices , 2002, IEEE Electron Device Letters.

[2]  T. Schulz,et al.  Impact of technology parameters on inverter delay of UTB-SOI CMOS , 2002, 2002 IEEE International SOI Conference.

[3]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[4]  V. Misra,et al.  Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).