DCT/IDCT processor design for high data rate image coding

Computation of the discrete cosine transform (DCT) and its inverse (IDCT) at a high data rate is considered. The issues involved in the design of special-purpose VLSI processors are discussed, and an 8*8 2-D DCT/IDCT processor chip that can be used for high rate image and video coding is presented. A recently published algorithm for computing the DCT and its inverse is outlined. The processor architecture based on the algorithm is presented. Details of functional units and special circuits are discussed. The 8*8 2-D DCT/IDCT processor chip measures 7.9*9.2 mm/sup 2/. It is designed using the MOSIS 2 mu m scalable CMOS technology. It takes 16-b inputs. uses 16-b internal memory for coefficients and data, and generates 16-b outputs. A single input line determines if the chip computes the DCT or the IDCT. The chip is highly pipelined with a latency of 127 cycles and a maximum delay time of 18 ns between any two pipeline stages. >

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