Thermal stress aware 3D-IC statistical static timing analysis

It is widely known that fabrication and thermal variations influence circuit delay. In three dimensional circuits (3D-ICs), due to the incorporation of through-silicon-vias (TSVs), thermal stress also becomes an increasing contributor to gate delay. As a result, thermal variations cause not only direct impact to the circuit parameters, they also cause 3D-IC stress variations resulting in an additional source of variability which needs to be accounted for in statistical static timing analysis (SSTA). In this paper, we study the impact (both direct and indirect - through thermal stress) of thermal variations on gate delay, and propose Monte Carlo (MC) simulation based fabrication, temperature and thermal stress variations aware SSTA methodology that accounts for this complex effect. We show that thermal stress variations cause extra -4~10% delay changes compared with the SSTA that only accounts for fabrication and direct thermal impacts, indicating that thermal stress should be considered together with direct temperature effect. We then develop a more efficient canonical thermal stress aware SSTA method that can achieve good accuracy and 843x speedup compared with MC based method.