High performance parallel computing. Final report, 1 January-31 December 1983

The accomplishments of the research project High Performance Parallel Computing for the year 1983 span algorithm formulation, paralle programming languages, basic software for the Texas Reconfigurable Array Computer, and validation of design concpets for the Texas Reconfigurable Array Computer (TRAC). Image processing, sorting, and time-dependent partial differential equations were subjects for algorithm formulation and analysis. Accomplishments in parallel programming include: substantial progress toward the implementation of two parallel programming environments, the Computation Structures Language, and a task level data flow programming system. The hardware prototype of TRAC made substantial progress towards stability. The state-of-the-art in reconfigurable switch-based architectures was advanced. A result of note is the demonstration of the integration of circuit switching and packet switching in a single interconnection network.