Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Surface channel strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moore's law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO/sub 2/ interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO/sub 2/ interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO/sub 2/ interface quality on MOSFET devices fabricated using a high-temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO/sub 2/ interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO/sub 2/ interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of /spl sim/ 5.0 nm is required to achieve a good strained Si/SiO/sub 2/ interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process.

[1]  I. S. Goh,et al.  Electrical properties of plasma-grown oxide on MBE-grown SiGe , 1995 .

[2]  B. Kang,et al.  Oxidation-induced traps near SiO2/SiGe interface , 1999 .

[3]  K. Rim,et al.  Fabrication and analysis of deep submicron strained-Si n-MOSFET's , 2000 .

[4]  P. Lundgren,et al.  Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures , 2003 .

[5]  Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers , 2001 .

[6]  E. G. Chester,et al.  Device and circuit performance of SiGe/Si MOSFETs , 2002 .

[7]  Goutam Kumar Dalapati,et al.  Gate dielectrics on strained-Si/SiGe heterolayers , 2004 .

[8]  D. Misra,et al.  Plasma process-induced band-gap modifications of a strained SiGe heterostructure , 1999 .

[9]  A. G. Cullis,et al.  Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching on device performance , 2002 .

[10]  Diffusion of Ge in Si1-xGex/Si single quantum wells in inert and oxidizing ambients , 2000 .

[11]  T. Tezuka,et al.  Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility , 2002, Digest. International Electron Devices Meeting,.

[12]  Jung Houn Yap,et al.  LETTER TO THE EDITOR: Film thickness constraints for manufacturable strained silicon CMOS , 2004 .

[13]  Keith A. Jenkins,et al.  Strained Si CMOS (SS CMOS) technology: Opportunities and challenges , 2003 .

[14]  L. Terman.  An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes , 1962 .

[15]  A. O'Neill,et al.  Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors , 2005 .

[16]  D. K. Nayak,et al.  Low‐field hole mobility of strained Si on (100) Si1−xGex substrate , 1994 .

[17]  Kyu-Hwan Shim,et al.  Effects of Si-cap layer thinning and Ge segregation on the characteristics of Si/SiGe/Si heterostructure pMOSFETs , 2002 .

[18]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[19]  D. Schroder.  Semiconductor Material and Device Characterization, 3rd Edition , 2005 .

[20]  N. Woods,et al.  Modified GSMBE for higher growth rate and non-selective growth , 2001 .

[21]  J. Welser,et al.  Strain dependence of the performance enhancement in strained-Si n-MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[22]  A. O'Neill,et al.  Optimisation of channel thickness in strained Si/SiGe MOSFETs , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

[23]  B. Meyerson,et al.  Oxidation studies of SiGe , 1989 .

[24]  W. A. Hill,et al.  A single-frequency approximation for interface-state density determination , 1980 .

[25]  D. Antoniadis,et al.  Deep submicron CMOS based on silicon germanium technology , 1996 .

[26]  Anthony O'Neill,et al.  SiGe virtual substrate N-channel heterojunction MOSFETs , 1999 .

[27]  A. Waite,et al.  Optimization of alloy composition for high-performance strained-Si-SiGeN-channel MOSFETs , 2004, IEEE Transactions on Electron Devices.

[28]  Douglas J. Paul,et al.  High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture , 2003 .

[29]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[30]  A. O'Neill,et al.  C–V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design , 2003 .

[31]  J.D. Plummer,et al.  Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces , 1980, IEEE Transactions on Electron Devices.

[32]  H. D. Banerjee,et al.  Interface properties and reliability of ultrathin oxynitride films grown on strained Si1−xGex substrates , 2003 .

[33]  D. Antoniadis,et al.  Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates , 2001 .

[34]  R. People,et al.  Calculation of critical layer thickness versus lattice mismatch for GexSi1−x/Si strained‐layer heterostructures , 1985 .

[35]  S. Ahmed,et al.  Strained silicon NMOS with nickel-silicide metal gate , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[36]  Sarah H. Olsen,et al.  Strained Si MOSFETs on relaxed SiGe platforms: performance and challenges , 2004 .

[37]  J. W. Matthews,et al.  Defects in epitaxial multilayers: I. Misfit dislocations* , 1974 .