Backside polishing detector: a new protection against backside attacks

Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this from the backside of the chip gives some advantages since no metal layers interfere between the hacker and the signals of interest. The bulk silicon is thinned from hundreds to some tens of micrometers in order to improve the performance of the attack. In this paper a backside polishing detector is presented that is sensitive to the thickness of the bulk silicon existing below the transistors, a numerical signature is generated which is related to this. The detector implements built-in self-surveillance techniques which protect it from being tampered.

[1]  Jean-Pierre Seifert,et al.  Differential Photonic Emission Analysis , 2013, COSADE.

[2]  Julie Ferrigno,et al.  When AES blinks: introducing optical side channel , 2008, IET Inf. Secur..

[3]  Said Hamdioui Yield improvement and test cost reduction for TSV based 3D stacked ICs , 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[4]  James D. Meindl,et al.  A physical alpha-power law MOSFET model , 1999 .

[5]  Jean-Pierre Seifert,et al.  Breaking and entering through the silicon , 2013, CCS.

[6]  C. Y. Chen,et al.  Mismatch Characterization of Ring Oscillators , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  s. zanero SMART CARD CONTENT SECURITY , 2002 .

[8]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[9]  Khaled Salah,et al.  TSV-based 3D integration fabrication technologies: An overview , 2014, 2014 9th International Design and Test Symposium (IDT).

[10]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[11]  Jasper G. J. van Woudenberg,et al.  Practical Optical Fault Injection on Secure Microcontrollers , 2011, 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography.

[12]  Jean-Jacques Quisquater,et al.  Faults, Injection Methods, and Fault Attacks , 2007, IEEE Design & Test of Computers.

[13]  Johannes Götzfried,et al.  ARMORED: CPU-Bound Encryption for Android-Driven ARM Devices , 2013, 2013 International Conference on Availability, Reliability and Security.

[14]  T. May,et al.  A New Physical Mechanism for Soft Errors in Dynamic Memories , 1978, 16th International Reliability Physics Symposium.