论文信息 - HIGH THROUGHPUT-LESS AREA EFFICIENT FPGA IMPLEMENTATION OF BLOCK CIPHER AES ALGORITHM

HIGH THROUGHPUT-LESS AREA EFFICIENT FPGA IMPLEMENTATION OF BLOCK CIPHER AES ALGORITHM

This paper addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. The area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of implementation.

M. SIRIN KUMARI | D. MAHESH KUMAR | Y. RAMA DEVI

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