Modest power savings for applications dominated by switching of large capacitive loads

A method for improving the power efficiency of conventional CMOS through charge storage and reuse is proposed and evaluated. The application of the method is specific to nodes within a circuit which are dominated by capacitive loads much larger than the gate capacitance of a minimum-sized device within the desired CMOS technology. An upper bound on power savings via the proposed method is given, and implementation and shortcomings of the method are discussed.