A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design

With the exponential reduction in scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupling, delay deterioration and crosstalk. This paper presents a timing-driven global routing algorithm with consideration of coupling effects and crosstalk avoidance. Our work differs from the existing ones in that we design a global routing "framework" which performs well in routablity, timing, and also facilitate the detailed routing in crosstalk avoidance. Experimental results on industrial circuits show that, the algorithm leads to substantial delay reduction and effective crosstalk elimination.

[1]  Xianlong Hong,et al.  TIGER: an efficient timing-driven global router for gate array and standard cell layout design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  N. Nettleton,et al.  Dense, performance directed, auto place and route , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  Yici Cai,et al.  A novel and efficient timing-driven global router for standard cell layout design based on critical network concept , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  Sachin S. Sapatnekar,et al.  A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Yu-Chung Lin,et al.  Minimum crosstalk channel routing with dogleg , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  Lei He,et al.  Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2000, ISPD '00.

[7]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[8]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[9]  Yici Cai,et al.  A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design , 2003, ASP-DAC '03.

[10]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[11]  Dongsheng Wang,et al.  Post global routing crosstalk risk estimation and reduction , 1996, ICCAD 1996.

[12]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[13]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[14]  Hai Zhou,et al.  An optimal algorithm for river routing with crosstalk constraints , 1996, ICCAD 1996.

[15]  Yici Cai,et al.  An efficient hierarchical timing-driven Steiner tree algorithm for global routing , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[16]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[17]  Sachin S. Sapatnekar,et al.  A timing-constrained algorithm for simultaneous global routing of multiple nets , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[18]  James D. Z. Ma,et al.  Towards global routing with RLC crosstalk constraints , 2002, DAC '02.

[19]  John Lillis,et al.  Table-lookup methods for improved performance-driven routing , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).