Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI

Abstract Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC 603 DFF and the C 2 MOS DFF are considered to be the overall best candidates of the nine. The pass gate DFF had the lowest energy consumption per cycle for frequencies lower than 500 kHz and for supply voltages below 400 mV. It was implemented with the smallest physical footprint and it proved to be functional down to the lowest operating voltage of 65 mV in the typical process corner. During Monte Carlo (MC) process and mismatch simulations it was also found that the pass gate DFF is least prone to variations in both minimal setup- and minimal hold-time. Race conditions, during mismatch variations, occurred for the flip-flop that is constructed from NAND and inverter based multiplexers. The pass gate DFF is outperformed slightly when it comes to D-Q-based power-delay product and more significantly when it comes to the maximum clock frequency. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop, these also had the lowest D-Q-based power-delay of 26% and 30% respectively of that of the worst-case S 2 CFF power-delay product.

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