RTL design validation, DFT and test pattern generation for high defects coverage

The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability Metrics, two approaches are combined: RTL DFT and TPG. RTL Design for Testability is illustrated through TPI (Test Point Insertion). RTL Test Pattern Generation is performed using the property that strong correlation exists between n-detection of RT-level faults and single detection of physical defects. The derived functional test leads to high Defects Coverage, DC, when the RTL description is synthesized into a physical layout. The proposed methodology enables tradeoff analysis, for different DFT solutions, or test pattern sequences. The resulting test patterns are, in fact, loosely deterministic patterns, suitable for low-cost BIST implementation. The usefulness of the methodology is ascertained using the mixed-level VeriDOS fault simulation tool and modules from the CMUDSP and TORCH ITC '99 benchmark circuits.

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