Analysis of Process Variation Effect on Clock Networks

In synchronous digital circuit, clock network is constructed to transfer clock signal from clock source to every clock sink element. The major objective of clock network synthesis is minimizing clock skew, which is the maximum difference of the arrival times of the clock signals to sink elements. As technology scaling continues, the process variation on clock network can cause unintended clock skew which leads to run-time timing violation. In this paper, we analysis the effect of process variation on two well known clock network structures, clock tree and clock mesh.