Gettering in silicon-on-insulator wafers: experimental studies and modelling

Buried oxide, which separates the device area from the substrate in silicon-on-insulator (SOI) wafers, forms a diffusion barrier for transition metals in silicon. The impact of this barrier on the efficiency of traditional gettering techniques for iron and copper is evaluated using computer modelling. Several parameters essential for the modelling, such as the diffusivity of iron in SiO2 and the segregation coefficient of iron and copper in SiO2, are verified experimentally. It is found that all available data for the diffusivity of iron in SiO2 (including data points from the literature and our own value of 1.4 × 10−13 cm s−2 at 1100 °C) could be fitted by the equation D(Fe in SiO2) = 2.2 × 10−2 × exp(−3.05 eV/kBT)(cm2 s−1). The solubility of iron in silicon dioxide was found to be 4.5 times to 5.5 times less than that in silicon at temperatures from 1020 °C to 1100 °C, which indicates that iron does not segregate in SiO2. The solubility of Cu in silicon dioxide was determined to be half of that in silicon at 1150 °C and 3.3 times higher than in silicon at 690 °C. Modelling of gettering using these parameters revealed that buried oxide prevents iron from diffusing to gettering sites in the substrate at typical processing temperatures, thus rendering the substrate gettering techniques inefficient. On the other hand, the diffusion barrier protects the device area from contamination from the backside of the wafer. Copper has sufficiently high diffusivity in SiO2 to diffuse through the buried oxide within a short time at 1000 °C; however, it may be difficult to remove copper from the device area because heavily doped areas of the devices could provide competitive gettering sites for copper. Possible gettering strategies for the SOI wafers are discussed.

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